| CPC H01L 29/7869 (2013.01) [G02F 1/136286 (2013.01); G09G 3/3233 (2013.01)] | 18 Claims |
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1. A display device, comprising:
a first transistor including:
a first active layer disposed on a substrate; and
a gate electrode disposed on the first active layer;
an insulation layer disposed on the gate electrode;
a second transistor including:
a lower gate electrode disposed on the insulation layer;
a second active layer disposed on the lower gate electrode, a first end portion of the second active layer being electrically connected to an end portion of the first active layer; and
an upper gate electrode disposed on the second active layer;
a lower gate signal line extending in a first direction, a portion of the lower gate signal line forming the lower gate electrode;
an upper gate signal line disposed on the lower gate signal line and extending in the first direction, a portion of the upper gate signal line forming the upper gate electrode; and
a first connection pattern disposed on the upper gate signal line and connecting the gate electrode and a second end portion of the second active layer, wherein
a first area in which the lower gate signal line and the first connection pattern overlap each other is within a second area in which the upper gate signal line and the first connection pattern overlap each other, in a plan view, and
a width of the upper gate sianal line overlapping the first connection pattern is greater than a width of the lower gate signal line overlapping the first connection pattern.
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