US 11,769,824 B2
Gallium nitride transistor with a doped region
Dong Seup Lee, McKinney, TX (US); Jungwoo Joh, Allen, TX (US); Pinghai Hao, Plano, TX (US); and Sameer Pendharkar, Allen, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Feb. 2, 2021, as Appl. No. 17/165,697.
Application 17/165,697 is a division of application No. 16/194,794, filed on Nov. 19, 2018, granted, now 10,964,803.
Prior Publication US 2021/0159329 A1, May 27, 2021
Int. Cl. H01L 29/778 (2006.01); H01L 21/265 (2006.01); H01L 29/06 (2006.01); H01L 29/20 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/08 (2006.01); H01L 29/423 (2006.01); H01L 29/10 (2006.01)
CPC H01L 29/7786 (2013.01) [H01L 21/2654 (2013.01); H01L 29/0603 (2013.01); H01L 29/0607 (2013.01); H01L 29/0843 (2013.01); H01L 29/2003 (2013.01); H01L 29/41775 (2013.01); H01L 29/66431 (2013.01); H01L 29/66462 (2013.01); H01L 29/0891 (2013.01); H01L 29/42316 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A method for fabricating a transistor, comprising:
forming a heterostructure over a substrate, the heterostructure including a gallium nitride (GaN) layer, and a GaN-based alloy layer disposed on the GaN layer and having a top side;
implanting dopants directly to the top side of the GaN-based alloy layer to form a doped region extending from the top side into the GaN layer in a drain access region; and
depositing source, drain, and gate contact structures that are supported by the GaN layer.