CPC H01L 29/7786 (2013.01) [H01L 21/2654 (2013.01); H01L 29/0603 (2013.01); H01L 29/0607 (2013.01); H01L 29/0843 (2013.01); H01L 29/2003 (2013.01); H01L 29/41775 (2013.01); H01L 29/66431 (2013.01); H01L 29/66462 (2013.01); H01L 29/0891 (2013.01); H01L 29/42316 (2013.01)] | 22 Claims |
1. A method for fabricating a transistor, comprising:
forming a heterostructure over a substrate, the heterostructure including a gallium nitride (GaN) layer, and a GaN-based alloy layer disposed on the GaN layer and having a top side;
implanting dopants directly to the top side of the GaN-based alloy layer to form a doped region extending from the top side into the GaN layer in a drain access region; and
depositing source, drain, and gate contact structures that are supported by the GaN layer.
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