US 11,769,753 B2
Thermally-optimized tunable stack in cavity package-on-package
George Vakanas, Tempe, AZ (US); Aastha Uppal, Chandler, AZ (US); Shereen Elhalawaty, Scottsdale, AZ (US); Aaron McCann, Queen Creek, AZ (US); Edvin Cetegen, Chandler, AZ (US); Tannaz Harirchian, Scottsdale, AZ (US); and Saikumar Jayaraman, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 31, 2018, as Appl. No. 16/51,065.
Prior Publication US 2020/0043894 A1, Feb. 6, 2020
Int. Cl. H01L 25/065 (2023.01); H01L 23/373 (2006.01); H01L 23/367 (2006.01); H01L 23/00 (2006.01); H10B 12/00 (2023.01)
CPC H01L 25/0657 (2013.01) [H01L 23/367 (2013.01); H01L 23/3736 (2013.01); H01L 24/49 (2013.01); H10B 12/00 (2023.02)] 11 Claims
OG exemplary drawing
 
1. An electronics package, comprising:
a package substrate;
a first die coupled to the package substrate, the first die having a bottommost surface above an uppermost surface of an entirety of the package substrate;
a second die over the first die, wherein the first die and the second die are electrically coupled to the package substrate with wire bonds;
a cavity through the package substrate, wherein the cavity is within a footprint of the first die; and
a thermal stack in the cavity, wherein the thermal stack directly physically contacts the first die, and wherein the thermal stack is within the footprint of the first die.