US 11,769,746 B2
Semiconductor package
Ae-Nee Jang, Seoul (KR); KyungSeon Hwang, Incheon (KR); and SunWon Kang, Seongnam-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Mar. 2, 2021, as Appl. No. 17/189,405.
Application 17/189,405 is a continuation of application No. 16/244,661, filed on Jan. 10, 2019, granted, now 10,943,881.
Application 16/244,661 is a continuation of application No. 15/375,196, filed on Dec. 12, 2016, granted, now 10,211,176, issued on Feb. 19, 2019.
Claims priority of application No. 10-2015-0183052 (KR), filed on Dec. 21, 2015.
Prior Publication US 2021/0183801 A1, Jun. 17, 2021
Int. Cl. H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 23/48 (2006.01)
CPC H01L 24/14 (2013.01) [H01L 21/563 (2013.01); H01L 23/481 (2013.01); H01L 24/05 (2013.01); H01L 24/10 (2013.01); H01L 24/11 (2013.01); H01L 24/12 (2013.01); H01L 24/13 (2013.01); H01L 24/73 (2013.01); H01L 24/03 (2013.01); H01L 24/06 (2013.01); H01L 2224/0345 (2013.01); H01L 2224/03912 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05022 (2013.01); H01L 2224/05025 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/05155 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05171 (2013.01); H01L 2224/05572 (2013.01); H01L 2224/05582 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05655 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/06102 (2013.01); H01L 2224/10125 (2013.01); H01L 2224/1147 (2013.01); H01L 2224/11462 (2013.01); H01L 2224/11849 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13025 (2013.01); H01L 2224/13082 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/13564 (2013.01); H01L 2224/13582 (2013.01); H01L 2224/14104 (2013.01); H01L 2224/14515 (2013.01); H01L 2224/14517 (2013.01); H01L 2224/26145 (2013.01); H01L 2224/73104 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/81203 (2013.01); H01L 2224/81815 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a substrate;
through-electrodes penetrating the substrate;
first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate, the first bumps being electrically connected to the through-electrodes, respectively;
at least one second bump disposed between the first bumps, the at least one second bump being electrically floated; and
an underfill covering the substrate, the first bumps, and the at least one second bump,
wherein the first bumps and the at least one second bump constitute one row in the first direction, and
wherein the at least one second bump is disposed at a higher level from the substrate than the first bumps.