US 11,769,743 B2
Semiconductor package
Gayoung Kim, Hwaseong-si (KR); and Hyungsun Jang, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Sep. 7, 2021, as Appl. No. 17/468,008.
Claims priority of application No. 10-2021-0014294 (KR), filed on Feb. 1, 2021.
Prior Publication US 2022/0246563 A1, Aug. 4, 2022
Int. Cl. H01L 23/00 (2006.01)
CPC H01L 24/08 (2013.01) [H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05009 (2013.01); H01L 2224/05557 (2013.01); H01L 2224/08059 (2013.01); H01L 2224/13021 (2013.01); H01L 2924/35121 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a semiconductor chip comprising a chip pad on a first surface of the semiconductor chip;
a first insulating layer arranged on the semiconductor chip and comprising an insulating hole exposing the chip pad;
a redistribution pattern comprising a redistribution via pattern arranged on an internal surface of the first insulating layer that is configured to define the insulating hole and on a surface of the chip pad, and a redistribution line pattern arranged on a surface of the first insulating layer to extend in a horizontal direction and comprising a first dummy hole;
an under bump metal (UBM) comprising a first UBM portion arranged on the redistribution via pattern and a second UBM portion extending from the first UBM portion to be arranged on the redistribution line pattern and comprising a second dummy hole overlapping the first dummy hole in a vertical direction; and
a connection terminal arranged on the UBM, and comprising a dummy portion configured to fill an internal portion of a dummy hole comprising the first dummy hole of the redistribution line pattern and the second dummy hole of the second UBM portion.