CPC H01L 21/76802 (2013.01) [H01L 21/76838 (2013.01)] | 17 Claims |
1. A method of manufacturing a semiconductor device, comprising:
forming a stack;
forming a preliminary stepped structure by patterning the stack;
forming a first stepped structure, a second stepped structure, and an opening located between the first stepped structure and the second stepped structure by etching the preliminary stepped structure;
forming a passivation layer that fills the opening and covers the first stepped structure; and
forming a third stepped structure by etching the second stepped structure using the passivation layer as an etching barrier.
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