CPC G11C 7/222 (2013.01) [G11C 7/1057 (2013.01); G11C 7/1063 (2013.01); G11C 7/1084 (2013.01); G11C 8/18 (2013.01); G11C 29/42 (2013.01); H03K 19/1737 (2013.01)] | 20 Claims |
1. A memory device, comprising:
a memory cell array configured to store data; and
a data output circuit configured to transmit a data signal to an external device, wherein the data output circuit includes:
a latch register configured to store the data read from the memory cell array;
a status register configured to store status data; and
a multiplexer configured to select first output data of the status register during a latency period and second output data of the latch register during a period subsequent to the latency period.
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