US 11,769,534 B2
Flexible memory system with a controller and a stack of memory
Joe M. Jeddeloh, Shoreview, MN (US); and Brent Keeth, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 19, 2022, as Appl. No. 17/947,680.
Application 17/947,680 is a continuation of application No. 17/340,681, filed on Jun. 7, 2021, granted, now 11,450,354.
Application 17/340,681 is a continuation of application No. 16/927,146, filed on Jul. 13, 2020, granted, now 11,031,049.
Application 16/927,146 is a continuation of application No. 16/279,590, filed on Feb. 19, 2019, granted, now 10,714,150.
Application 16/279,590 is a continuation of application No. 15/620,490, filed on Jun. 12, 2017, granted, now 10,283,172.
Application 15/620,490 is a continuation of application No. 13/919,503, filed on Jun. 17, 2013, granted, now 9,679,615.
Claims priority of provisional application 61/791,182, filed on Mar. 15, 2013.
Prior Publication US 2023/0080130 A1, Mar. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 5/06 (2006.01); G11C 5/14 (2006.01); G11C 7/10 (2006.01); H01L 25/065 (2023.01); G11C 5/02 (2006.01); H01L 25/18 (2023.01); G11C 11/4063 (2006.01)
CPC G11C 5/066 (2013.01) [G11C 5/025 (2013.01); G11C 5/14 (2013.01); G11C 7/10 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); G11C 11/4063 (2013.01); H01L 2224/16225 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2924/0002 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/15311 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method, comprising:
accessing multiple DRAM memory die stacked above a substrate,
wherein each die includes multiple partitions which each operate independently from other partitions of the multiple partitions on the die, and
wherein vertically interconnected partitions of two or more stacked memory die are interconnected to form respective memory assemblies; and
through use of control logic supported by the substrate,
exchanging first data with a memory assembly through first data interface contacts,
exchanging second data with a second memory assembly through second data interface contacts, and
providing command signals to both of the first and second memory assemblies through shared command interface contacts in communication with both the first and second memory assemblies.