CPC G11C 5/066 (2013.01) [G11C 5/025 (2013.01); G11C 5/14 (2013.01); G11C 7/10 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); G11C 11/4063 (2013.01); H01L 2224/16225 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2924/0002 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/15311 (2013.01)] | 19 Claims |
1. A method, comprising:
accessing multiple DRAM memory die stacked above a substrate,
wherein each die includes multiple partitions which each operate independently from other partitions of the multiple partitions on the die, and
wherein vertically interconnected partitions of two or more stacked memory die are interconnected to form respective memory assemblies; and
through use of control logic supported by the substrate,
exchanging first data with a memory assembly through first data interface contacts,
exchanging second data with a second memory assembly through second data interface contacts, and
providing command signals to both of the first and second memory assemblies through shared command interface contacts in communication with both the first and second memory assemblies.
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