US 11,768,967 B2
Address verification for direct memory access requests
Wei Ze Liu, Spring, TX (US); and Monji G Jabori, Spring, TX (US)
Assigned to HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P., Spring, TX (US)
Appl. No. 16/966,314
Filed by HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P., Spring, TX (US)
PCT Filed Mar. 15, 2018, PCT No. PCT/US2018/022583
§ 371(c)(1), (2) Date Aug. 25, 2020,
PCT Pub. No. WO2019/177608, PCT Pub. Date Sep. 19, 2019.
Prior Publication US 2023/0195946 A1, Jun. 22, 2023
Int. Cl. G06F 21/79 (2013.01); G06F 21/85 (2013.01)
CPC G06F 21/79 (2013.01) [G06F 21/85 (2013.01)] 15 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a memory;
a processor executing instructions stored in the memory to:
receive a direct memory access (DMA) request from a driver of a device, wherein:
the DMA request comprises an address and an identifier (ID) of the device that uniquely identifies the device; and
the device is a bus mastering (BM) device, wherein the BM device is a trusted device, and wherein the BM device is to:
access a range of addresses using the ID of the device;
determine whether the address is in the range of addresses; and
process the DMA request responsive to verifying that the address is in the range of addresses.