CPC G06F 21/602 (2013.01) [G06F 9/30043 (2013.01); G06F 9/30101 (2013.01); G06F 9/30178 (2013.01); G06F 9/321 (2013.01); G06F 9/45558 (2013.01); G06F 9/48 (2013.01); G06F 9/5016 (2013.01); G06F 12/0207 (2013.01); G06F 12/0646 (2013.01); G06F 12/0811 (2013.01); G06F 12/0875 (2013.01); G06F 12/0897 (2013.01); G06F 12/1408 (2013.01); G06F 12/1458 (2013.01); G06F 12/1466 (2013.01); G06F 21/12 (2013.01); G06F 21/6227 (2013.01); G06F 21/72 (2013.01); G06F 21/79 (2013.01); H04L 9/0637 (2013.01); H04L 9/0822 (2013.01); H04L 9/0861 (2013.01); H04L 9/0869 (2013.01); H04L 9/0894 (2013.01); H04L 9/14 (2013.01); G06F 2009/45587 (2013.01); G06F 2212/1052 (2013.01); H04L 2209/125 (2013.01)] | 20 Claims |
1. A processor comprising:
a decoder to decode a first instruction requesting a memory heap operation; and
circuitry to implement a heap manager, the heap manager to:
responsive to the first instruction requesting the memory heap operation:
defragment multiple data blocks to form a data block of a memory heap;
combine tag histories of the multiple data blocks to form a tag history for the data block, wherein the tag histories comprise a first tag history comprising at least one tag previously assigned to a first data block of the multiple data blocks and a second tag history comprising at least one tag previously assigned to a second data block of the multiple data blocks;
assign a tag to the data block, wherein assigning the tag comprises verification that the tag does not match any tags of the tag history for the data block; and
provide the assigned tag and a reference to a location of the data block.
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