US RE50,596 E1
On-chip reliability monitor and method
John A. Fifield, Underhill, VT (US); Eric Hunt-Schroeder, Essex Junction, VT (US); and Mark D. Jacunski, Colchester, VT (US)
Assigned to MARVELL ASIA PTE LTD, Singapore (SG)
Filed by MARVELL ASIA PTE, LTD., Singapore (SG)
Filed on Sep. 29, 2021, as Appl. No. 17/488,996.
Application 17/488,996 is a reissue of application No. 15/903,231, filed on Feb. 23, 2018, granted, now 10,429,434, issued on Oct. 1, 2019.
Int. Cl. G01R 31/26 (2020.01); G01R 31/28 (2006.01)
CPC G01R 31/2642 (2013.01) [G01R 31/2875 (2013.01); G01R 31/2879 (2013.01)] 37 Claims
OG exemplary drawing
 
1. An integrated circuit chip comprising:
a substrate; and
a reliability monitor on the substrate and comprising:
a test circuit comprising a test device;
a reference circuit comprising a reference device [ ; wherein the test device and the reference device are duplicates of a function device of the integrated circuit chip] ; and
a comparator circuit connected to the test circuit and the reference circuit,
wherein, when the integrated circuit chip is powered on, the reliability monitor is alternatingly operable in stress and test modes,
wherein, during each stress mode, the test device is subjected to stress conditions that emulate operating conditions of a [ the ] functional device and the reference device is unstressed, and
wherein, during each test mode, the stress conditions are removed from the test device and the comparator circuit compares a test parameter of the test device to a reference parameter of the reference device and outputs a status signal based on a difference between the test parameter and the reference parameter [ , and
when the status signal output by the reliability monitor switches values, a second reliability monitor on the integrated circuit chip is enabled so that the second reliability monitor alternatingly operates in stress and test modes] .