US 12,426,520 B2
Resistive random access memory device and fabrication method thereof
Wen-Jen Wang, Tainan (TW); Yu-Huan Yeh, Hsinchu (TW); and Chuan-Fu Wang, Miaoli County (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Feb. 21, 2023, as Appl. No. 18/112,483.
Claims priority of application No. 112102908 (TW), filed on Jan. 30, 2023.
Prior Publication US 2024/0260490 A1, Aug. 1, 2024
Int. Cl. H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC H10N 70/8418 (2023.02) [H10N 70/011 (2023.02); H10N 70/24 (2023.02); H10N 70/8833 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A resistive memory device, comprising:
a substrate;
a dielectric layer disposed on the substrate;
a conductive via disposed in the dielectric layer; and
a memory stack structure disposed on the conductive via and the dielectric layer, wherein the memory stack structure comprises a bottom electrode layer, a resistive switching layer on the bottom electrode layer, and a top electrode layer on the resistive switching layer, wherein the top electrode layer comprises at least two physically separated sub-electrode portions.