US 12,426,519 B2
Memory devices
Hung-Li Chiang, Taipei (TW); Jer-Fu Wang, Taipei (TW); Chao-Ching Cheng, Hsinchu (TW); and Tzu-Chiang Chen, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 21, 2024, as Appl. No. 18/669,541.
Application 18/363,751 is a division of application No. 17/371,123, filed on Jul. 9, 2021, granted, now 11,903,334, issued on Feb. 13, 2024.
Application 18/669,541 is a continuation of application No. 18/363,751, filed on Aug. 2, 2023, granted, now 12,022,752.
Claims priority of provisional application 63/175,539, filed on Apr. 15, 2021.
Prior Publication US 2024/0315152 A1, Sep. 19, 2024
Int. Cl. H10N 70/00 (2023.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01)
CPC H10N 70/8413 (2023.02) [H10B 63/20 (2023.02); H10N 70/011 (2023.02); H10N 70/231 (2023.02); H10N 70/826 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a first conductive feature disposed over a substrate;
a memory layer disposed over the first conductive feature;
a buffer layer disposed between the first conductive feature and the memory layer;
a dielectric cap layer disposed aside the buffer layer, wherein the memory layer is in contact with the buffer layer and the dielectric cap layer;
a bottom electrode disposed within the buffer layer and in physical contact with the first conductive feature and the memory layer; and
a top electrode disposed over the memory layer,
wherein a width of the memory layer is greater than a width of the buffer layer.