| CPC H10N 70/235 (2023.02) [H10B 63/20 (2023.02); H10N 70/011 (2023.02); H10N 70/841 (2023.02)] | 16 Claims | 

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               1. A memory cell, comprising: 
            a substrate; 
                a first electrode layer on top of the substrate; 
                a conductive oxide diffusion barrier layer on top of the first electrode, wherein the conductive oxide diffusion barrier comprises gallium (Ga) doped zinc oxide (ZnO) and is configured to prevent a diffusion of the first electrode layer into a polycrystalline silicon diode on top of the conductive oxide diffusion barrier, wherein the polycrystalline silicon diode is laser annealed; and 
                a phase change material (PCM) layer on top of the polycrystalline silicon diode; and 
                a second electrode on top of the PCM layer. 
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