US 12,426,467 B2
Display apparatus and electronic device comprising first capacitor and second capacitor
Takeya Hirose, Kanagawa (JP); and Hideaki Shishido, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., (JP)
Appl. No. 17/787,654
Filed by Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (JP)
PCT Filed Dec. 11, 2020, PCT No. PCT/IB2020/061798
§ 371(c)(1), (2) Date Jun. 21, 2022,
PCT Pub. No. WO2021/130585, PCT Pub. Date Jul. 1, 2021.
Claims priority of application No. 2019-235131 (JP), filed on Dec. 25, 2019; and application No. 2020-067214 (JP), filed on Apr. 3, 2020.
Prior Publication US 2022/0416008 A1, Dec. 29, 2022
Int. Cl. H01L 29/08 (2006.01); H10K 59/121 (2023.01); H10K 59/131 (2023.01)
CPC H10K 59/1315 (2023.02) [H10K 59/1213 (2023.02); H10K 59/1216 (2023.02)] 11 Claims
OG exemplary drawing
 
1. A display apparatus comprising a pixel portion comprising a plurality of pixels, a first wiring, a first scan line, a second scan line, a third scan line, and a signal line,
wherein the pixels each comprise a light-emitting device, a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, and a second capacitor,
wherein one electrode of the light-emitting device is electrically connected to one of a source and a drain of the first transistor, one of a source and a drain of the second transistor, and one electrode of the first capacitor,
wherein a gate of the second transistor is electrically connected to the other electrode of the first capacitor, one of a source and a drain of the third transistor, one of a source and a drain of the fourth transistor, and one electrode of the second capacitor,
wherein the other electrode of the second capacitor is electrically connected to the other of the source and the drain of the second transistor,
wherein the other of the source and the drain of the first transistor and the other of the source and the drain of the fourth transistor are each electrically connected to the first wiring,
wherein a gate of the first transistor is electrically connected to the first scan line,
wherein a gate of the third transistor is electrically connected to the second scan line,
wherein a gate of the fourth transistor is electrically connected to the third scan line,
wherein the other of the source and the drain of the third transistor is electrically connected to the signal line, and
wherein one frame period of each of the pixels comprises a period in which the first transistor and the fourth transistor are each in a conduction state.