US 12,426,419 B2
Display panel and display apparatus
Mengmeng Zhang, Wuhan (CN); Yue Li, Wuhan (CN); and Jing Huang, Shanghai (CN)
Assigned to WUHAN TIANMA MICROELECTRONICS CO., LTD., Wuhan (CN); and Wuhan Tianma Microelectronics Co., Ltd. Shanghai Branch, Shanghai (CN)
Filed by WUHAN TIANMA MICROELECTRONICS CO., LTD., Wuhan (CN); and Wuhan Tianma Microelectronics Co., Ltd. Shanghai Branch, Shanghai (CN)
Filed on Aug. 24, 2022, as Appl. No. 17/821,891.
Claims priority of application No. 202210570380.7 (CN), filed on May 24, 2022.
Prior Publication US 2023/0387366 A1, Nov. 30, 2023
Int. Cl. H10H 20/857 (2025.01); H10H 20/831 (2025.01); H10H 29/14 (2025.01)
CPC H10H 20/857 (2025.01) [H10H 20/8312 (2025.01); H10H 29/142 (2025.01)] 23 Claims
OG exemplary drawing
 
1. A display panel, comprising:
a substrate; and
an array layer located at a side of the substrate,
wherein the array layer comprises:
pixel circuits each comprising transistors, wherein each of the transistors comprises an active layer, wherein the active layer comprises a channel; and the transistors comprise a driving transistor and a first switching transistor; and
at least first vias, wherein in a direction perpendicular to the substrate, a distance between one of the at least first vias and the channel of the driving transistor of one of the pixel circuits that is closest to the one of the at least first vias is greater than a preset distance, and a distance between an edge of of the at least first vias and an edge of the channel of the first switching transistor of one of the pixel circuits that is closest to the one first via is smaller than the preset distance;
wherein the first switching transistor comprises a threshold compensation transistor electrically connected between a second electrode of the driving transistor and a gate of the driving transistor;
wherein the at least first vias comprise a second sub-via; and, in the direction perpendicular to the substrate, a distance between the second sub-via and the channel of the driving transistor closest to the second sub-via is greater than the preset distance, and a distance between the edge of the second sub-via and the edge of the channel of the threshold compensation transistor closest to the second sub-via is smaller than the preset distance;
wherein the threshold compensation transistor is electrically connected to the gate of the driving transistor through a second connection line and a third connection line; and
wherein the second sub-via comprises a second connection via electrically connected between the second connection line and the third connection line.