US 12,426,413 B2
Circuit and system integration onto a microdevice substrate
Gholamreza Chaji, Waterloo (CA); Ehsanollah Fathi, Waterloo (CA); Bahareh Sadeghimakki, Kitchener (CA); and Hossein Zamani Siboni, Waterloo (CA)
Assigned to VueReal Inc., Waterloo (CA)
Filed by VueReal Inc., Waterloo (CA)
Filed on Jan. 30, 2023, as Appl. No. 18/161,318.
Application 18/161,318 is a division of application No. 16/542,026, filed on Aug. 15, 2019.
Application 16/542,026 is a continuation in part of application No. 15/892,523, filed on Feb. 9, 2018, abandoned.
Claims priority of provisional application 62/808,578, filed on Feb. 21, 2019.
Claims priority of provisional application 62/768,812, filed on Nov. 16, 2018.
Claims priority of provisional application 62/746,300, filed on Oct. 16, 2018.
Claims priority of provisional application 62/482,939, filed on Apr. 7, 2017.
Claims priority of provisional application 62/456,739, filed on Feb. 9, 2017.
Prior Publication US 2023/0178528 A1, Jun. 8, 2023
Int. Cl. H10H 20/814 (2025.01); H01L 25/075 (2006.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10H 20/84 (2025.01); H10H 20/851 (2025.01); H10H 20/852 (2025.01); H10H 20/856 (2025.01); H10H 20/857 (2025.01); H10H 20/01 (2025.01)
CPC H10H 20/852 (2025.01) [H01L 25/0753 (2013.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10H 20/84 (2025.01); H10H 20/8514 (2025.01); H10H 20/856 (2025.01); H10H 20/857 (2025.01); H10H 20/0361 (2025.01); H10H 20/0363 (2025.01); H10H 20/0364 (2025.01)] 4 Claims
OG exemplary drawing
 
1. An optoelectronic device comprising:
a device substrate;
a plurality of layers on a top surface of the device substrate, the plurality of layers having a top layer and a bottom layer, each layer of the plurality of layers having exposed side surfaces, the plurality of layers including one or more conductive layers and one or more active layers;
one or more extension layers surrounding the exposed side surfaces of at least the one or more active layers of the plurality of layers, the one or more extension layers being oblique to the top surface of the device substrate, at least one of the one or more extension layers contacting the device substrate;
a bonding pad coupled to the bottom layer and/or the top layer and extending over at least one of the one or more extension layers; and
a dielectric layer formed around the bonding pad and extending over a top surface of the one or more extension layers, wherein the dielectric layer is a distinct layer from the one or more extension layers and the dielectric layer does not contact exposed side surfaces of the one or more extension layers.