US 12,426,409 B2
Point source type light-emitting diode and manufacturing method thereof
Masatoshi Iwata, Akita (JP); and Shinya Shoji, Akita (JP)
Assigned to DOWA Electronics Materials Co., Ltd., Tokyo (JP)
Appl. No. 17/593,769
Filed by DOWA Electronics Materials Co., Ltd., Tokyo (JP)
PCT Filed Mar. 23, 2020, PCT No. PCT/JP2020/012734
§ 371(c)(1), (2) Date Sep. 24, 2021,
PCT Pub. No. WO2020/196411, PCT Pub. Date Oct. 1, 2020.
Claims priority of application No. 2019-059295 (JP), filed on Mar. 26, 2019; and application No. 2020-048945 (JP), filed on Mar. 19, 2020.
Prior Publication US 2022/0190199 A1, Jun. 16, 2022
Int. Cl. H10H 20/816 (2025.01); H10H 20/01 (2025.01); H10H 20/824 (2025.01); H10H 20/832 (2025.01)
CPC H10H 20/8162 (2025.01) [H10H 20/013 (2025.01); H10H 20/824 (2025.01); H10H 20/835 (2025.01); H10H 20/032 (2025.01)] 7 Claims
OG exemplary drawing
 
1. A point source type light-emitting diode comprising:
a support substrate;
a metal layer on the support substrate,
the metal layer having a light reflecting surface;
a current narrowing layer on the metal layer;
a III-V compound semiconductor laminate on the current narrowing layer,
the III-V compound semiconductor laminate including
a p-type semiconductor layer,
an active layer on the p-type semiconductor layer,
an n-type semiconductor layer on the active layer; and
a top electrode on the III-V compound semiconductor laminate, wherein
the top electrode has an opening for ejecting light emitted by the active layer,
the current narrowing layer includes a dielectric layer having a through hole and an intermediate electrode provided in the through hole, and the intermediate electrode electrically connects between the p-type semiconductor layer and the metal layer,
in a projection plane in which the current narrowing layer including the intermediate electrode is projected vertically onto the top electrode, the opening encloses the intermediate electrode, and the dielectric layer encloses the top electrode,
the light reflecting surface covers inclined surfaces of a mesa structure of the p-type semiconductor layer and the active layer via the dielectric layer, and
a thickness of the p-type semiconductor layer is 0.5 μm or more and 3.3 μm or less.