| CPC H10F 39/811 (2025.01) [H10F 39/199 (2025.01); H10F 39/807 (2025.01)] | 20 Claims |
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1. An image sensor, comprising:
a first semiconductor chip comprising a first semiconductor substrate disposed on a first wiring layer in a thickness direction of the image sensor;
a pixel region and a peripheral region adjacent to the pixel region disposed in the first semiconductor substrate, the pixel region comprising:
an active pixel region and a dummy pixel region at least partially surrounding the active pixel region; and
a plurality of pixels arranged in an array structure in the active pixel region and the dummy pixel region, the array structure being disposed perpendicular to the thickness direction, the plurality of pixels being separated from one another by deep trench isolations (DTIs) extending through a thickness of the first semiconductor substrate;
a second semiconductor chip attached to the first semiconductor chip through an adhesive layer, the second semiconductor chip including logic elements and a second wiring layer;
a backside contact configured to apply a negative (−) voltage to a conductive layer of a corresponding one of the DTIs, the backside contact being disposed in the dummy pixel region, the backside contact extending through the thickness of the first semiconductor substrate and including a side surface extending along the thickness direction, wherein the backside contact extends through the corresponding one of the DTIs such that the side surface of the backside contact is in contact with the conductive layer of the corresponding one of the DTIs within the first semiconductor substrate; and
a through via formed in the peripheral region and configured to connect a first wiring line of the first wiring layer with a second wiring line of the second wiring layer.
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