US 12,426,356 B2
Semiconductor device structure with hybrid fins
Jin-Aun Ng, Hsinchu (TW); Kuo-Cheng Chiang, Zhubei (TW); Hung-Li Chiang, Taipei (TW); Tzu-Chiang Chen, Hsinchu (TW); and I-Sheng Chen, Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jul. 5, 2022, as Appl. No. 17/857,786.
Application 17/857,786 is a continuation of application No. 16/728,719, filed on Dec. 27, 2019, granted, now 11,398,476.
Application 16/728,719 is a continuation in part of application No. 15/981,167, filed on May 16, 2018, granted, now 10,756,089, issued on Aug. 25, 2020.
Prior Publication US 2022/0336454 A1, Oct. 20, 2022
Int. Cl. H10D 84/83 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01)
CPC H10D 84/834 (2025.01) [H10D 84/0128 (2025.01); H10D 84/0158 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device structure, comprising:
a substrate;
a plurality of nanostructures over the substrate;
a semiconductor structure over the substrate, wherein the semiconductor structure comprises a lower portion and a protruding portion above the lower portion, and a top and a bottom of one of the nanostructures are vertically between opposite ends of the protruding portion;
an isolation structure surrounding the lower portion of the semiconductor structure; and
a metal gate stack wrapped around the nanostructures, wherein the metal gate stack comprises a gate dielectric layer, the gate dielectric layer has a first portion wrapped around a bottommost nanostructure of the nanostructures and a second portion extending along a top surface of the isolation structure, and the first portion is adjacent to the second portion, wherein the metal gate stack is wrapped around the protruding portion of the semiconductor structure, the metal gate stack further comprises a work function layer, and the work function layer is prevented from being between a bottommost surface of the protruding portion of the semiconductor structure and the substrate by the gate dielectric layer.