| CPC H10D 84/038 (2025.01) [H01L 21/32139 (2013.01); H10D 84/013 (2025.01); H10D 84/0151 (2025.01); H10D 84/0158 (2025.01); H10D 84/834 (2025.01)] | 20 Claims |
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1. A method, comprising:
forming a semiconductor fin over a substrate;
forming first, second, and third gate structures over the substrate and crossing the semiconductor fin;
forming first and second epitaxial source/drain structures over the semiconductor fin and on opposite sides of the first gate structure, and forming third and fourth source/drain epitaxial structures over the semiconductor fin and on opposite sides of the third gate structure;
forming first gate spacers, second gate spacers, third gate spacers on opposite sidewalls of the first, second, and third gate structures, respectively;
forming a first hard mask over the first, second, and third gate structures;
patterning the first hard mask to form a first opening;
etching a portion of the second gate structure and a portion of the semiconductor fin through the first opening of the first hard mask to form a recess; and
forming a dielectric layer in the recess, wherein a dielectric constant of the dielectric layer is lower than a dielectric constant of silicon oxide.
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