US 12,426,347 B2
Multi-gate transistor channel height adjustment
Pei-Ling Kao, Tainan (TW); You-Ting Lin, Miaoli County (TW); Chih-Chung Chang, Nantou County (TW); Jiun-Ming Kuo, Taipei (TW); and Yuan-Ching Peng, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on May 4, 2022, as Appl. No. 17/736,454.
Claims priority of provisional application 63/219,903, filed on Jul. 9, 2021.
Prior Publication US 2023/0017945 A1, Jan. 19, 2023
Int. Cl. H10D 84/03 (2025.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/3115 (2006.01); H01L 21/32 (2006.01); H01L 21/324 (2006.01); H10D 30/01 (2025.01); H10D 30/60 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/85 (2025.01)
CPC H10D 84/038 (2025.01) [H01L 21/0259 (2013.01); H01L 21/31111 (2013.01); H01L 21/31116 (2013.01); H01L 21/31155 (2013.01); H01L 21/32 (2013.01); H01L 21/324 (2013.01); H10D 30/031 (2025.01); H10D 30/611 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/017 (2025.01); H10D 84/0167 (2025.01); H10D 84/0188 (2025.01); H10D 84/85 (2025.01); H10D 30/024 (2025.01); H10D 84/0193 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
providing a semiconductor substrate having a first region and a second region;
forming a doped region with dopants in the first region of the semiconductor substrate;
epitaxially growing a semiconductor layer above the semiconductor substrate;
patterning the semiconductor layer to form a first fin in the first region and a second fin in the second region;
depositing a dielectric material layer on sidewalls of the first and second fins;
after the forming of the doped region, performing an anneal process in driving the dopants into the dielectric material layer, such that a dopant concentration in the dielectric material layer in the first region is higher than that in the second region; and
performing an etching process to recess the dielectric material layer, thereby exposing the sidewalls of the first and second fins, wherein a top surface of the recessed dielectric material layer in the first region is lower than that in the second region.