US 12,426,342 B2
Low germanium, high boron silicon rich capping layer for PMOS contact resistance thermal stability
Debaleena Nandi, Hillsboro, OR (US); Cory Bomberger, Portland, OR (US); Gilbert Dewey, Beaverton, OR (US); Anand S. Murthy, Portland, OR (US); Mauro Kobrinsky, Portland, OR (US); Rushabh Shah, Hillsboro, OR (US); Chi-Hing Choi, Portland, OR (US); Harold W. Kennel, Portland, OR (US); Omair Saadat, Beaverton, OR (US); Adedapo A. Oni, North Plains, OR (US); Nazila Haratipour, Portland, OR (US); and Tahir Ghani, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 25, 2021, as Appl. No. 17/359,327.
Prior Publication US 2022/0416050 A1, Dec. 29, 2022
Int. Cl. H10D 64/62 (2025.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 62/832 (2025.01)
CPC H10D 64/62 (2025.01) [H10D 30/6211 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 62/151 (2025.01); H10D 62/832 (2025.01)] 8 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a semiconductor channel;
a gate stack over the semiconductor channel;
a source region on a first end of the semiconductor channel;
a drain region on a second end of the semiconductor channel; and
a barrier layer over the source region, wherein the barrier layer comprises titanium, silicon, germanium, and boron throughout an entirety of the barrier layer.