| CPC H10D 64/2527 (2025.01) [H10D 30/63 (2025.01); H10D 62/126 (2025.01); H10D 64/518 (2025.01); H10D 84/837 (2025.01)] | 9 Claims |
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1. A semiconductor device that is a facedown mountable, chip-size-package type semiconductor device, the semiconductor device comprising:
a semiconductor layer;
a metal layer provided in contact with a back surface of the semiconductor layer;
a first vertical metal-oxide-semiconductor (MOS) transistor provided in a first area of the semiconductor layer;
a second vertical MOS transistor provided in a second area of the semiconductor layer, the second area being adjacent to the first area in a plan view of the semiconductor device;
a first gate pad and 2n+1 first source pads of the first vertical MOS transistor that are provided at positions within the first area in the plan view, on a top surface of the semiconductor device, n being an integer greater than or equal to 1; and
a second gate pad and 2n+1 second source pads of the second vertical MOS transistor that are provided at positions within the second area in the plan view, on the top surface of the semiconductor device, wherein
on a same side as the back surface, the semiconductor layer includes a semiconductor substrate that is a common drain region shared by the first vertical MOS transistor and the second vertical MOS transistor,
in the plan view,
the semiconductor layer has a shape of a rectangle having a first side, a second side, a third side, and a fourth side, the first side and the second side extending in a first direction and having an equal length, the third side and the fourth side extending in a second direction orthogonal to the first direction and having an equal length that is a length less than or equal to the equal length of the first side and the second side,
the first area and the second area are one and an other of two equal halves of an area of the semiconductor layer,
the third side is included in a perimeter of the first area, and the fourth side is included in a perimeter of the second area,
a boundary line between the first area and the second area is crank-shaped by connecting an entirety of a third segment, an entirety of a first segment, an entirety of a fourth segment, an entirety of a second segment, and an entirety of a fifth segment in order stated, from one end of the boundary line toward an other end of the boundary line, the first segment and the second segment extending in a straight line in the first direction, the third segment, the fourth segment, and the fifth segment extending in a straight line in the second direction, the boundary line monotonously changing in the first direction and the second direction from the one end toward the other end,
a length of the first segment is equal to a length of the second segment,
a length of the third segment is equal to a length of the fifth segment,
the one end of the boundary line is on the first side, and the other end of the boundary line is on the second side,
the fourth segment is on a virtual center line of the semiconductor layer that divides the area of the semiconductor layer into two equal halves in the plan view and extends in a straight line in the second direction,
the first gate pad is circular, a center of the first gate pad is on the virtual center line, and no other pads are present between the first gate pad and the second side,
the second gate pad is circular and has a diameter identical to a diameter of the first gate pad, a center of the second gate pad is on the virtual center line, and no other pads are present between the second gate pad and the first side,
the 2n+1 first source pads and the 2n+1 second source pads each have a shape of an obround whose longitudinal direction matches the second direction, and the 2n+1 first source pads and the 2n+1 second source pads have an equal width in a lateral direction,
the 2n+1 first source pads include a first closest source pad closest to the fourth segment and 2n first non-closest source pads not closest to the fourth segment,
the first closest source pad is so disposed that an axis of line symmetry, extending in the longitudinal direction, of the first closest source pad matches a first closest equal-interval line closest to the fourth segment among n+1 first equal-interval lines that are virtual lines extending in the second direction in the first area and arranged at equal intervals in the first direction,
the 2n first non-closest source pads are so disposed that with regard to each of n first non-closest equal-interval lines that are lines except the first closest equal-interval line included in the n+1 first equal-interval lines, axes of line symmetry, extending in the longitudinal direction, of two first non-closest source pads among the 2n first non-closest source pads match the first non-closest equal-interval line,
the 2n+1 second source pads include a second closest source pad closest to the fourth segment and 2n second non-closest source pads not closest to the fourth segment,
the second closest source pad is so disposed that an axis of line symmetry, extending in the longitudinal direction, of the second closest source pad matches a second closest equal-interval line closest to the fourth segment among n+1 second equal-interval lines that are virtual lines extending in the second direction in the second area and arranged at equal intervals in the first direction,
the 2n second non-closest source pads are so disposed that with regard to each of n second non-closest equal-interval lines that are lines except the second closest equal-interval line included in the n+1 second equal-interval lines, axes of line symmetry, extending in the longitudinal direction, of two second non-closest source pads among the 2n second non-closest source pads match the second non-closest equal-interval line, and
the 2n+1 first source pads and the 2n+1 second source pads are symmetrical with respect to the virtual center line as an axis of line symmetry.
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