	US 12,426,335 B2
	Reducing k values of dielectric films through anneal
Wen-Kai Lin, Hsinchu (TW); Che-Hao Chang, Hsinchu (TW); Chi On Chui, Hsinchu (TW); Yung-Cheng Lu, Hsinchu (TW); and Szu-Ying Chen, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 7, 2023, as Appl. No. 18/366,460.
Application 18/366,460 is a division of application No. 17/333,592, filed on May 28, 2021, granted, now 12,206,012.
Claims priority of provisional application 63/142,546, filed on Jan. 28, 2021.
Prior Publication US 2024/0021706 A1, Jan. 18, 2024
Int. Cl. H10D 64/01 (2025.01); H01L 21/02 (2006.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/23 (2025.01)

CPC H10D 64/018 (2025.01) [H01L 21/0228 (2013.01); H10D 30/6735 (2025.01); H10D 62/118 (2025.01); H10D 64/01 (2025.01); H10D 64/017 (2025.01); H10D 64/258 (2025.01)]

20 Claims

1. A method comprising:

forming a first semiconductor layer;

forming a second semiconductor layer over and contacting the first semiconductor layer;

laterally recessing the second semiconductor layer to form a lateral recess overlapping the first semiconductor layer; and

forming a low-k inner spacer in the lateral recess, wherein the forming the low-k inner spacer comprises:

depositing a high-k dielectric layer extending into the lateral recess; and

performing a treatment process to convert the high-k dielectric layer into a low-k dielectric layer; and

etching the low-k dielectric layer to remove portions of the low-k dielectric layer outside of the lateral recess.