| CPC H10D 64/017 (2025.01) [H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 30/6219 (2025.01); H10D 30/797 (2025.01); H10D 62/021 (2025.01); H10D 62/116 (2025.01); H10D 62/151 (2025.01); H10D 64/516 (2025.01); H10D 84/013 (2025.01); H10D 84/0135 (2025.01); H10D 84/0144 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01)] | 20 Claims |
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1. A semiconductor device, comprising:
a fin extending from a substrate, the fin having an upper surface, a first sidewall, and a second sidewall;
an isolation region along a sidewall of the fin, the fin extending higher than an upper surface of the isolation region;
a gate structure over the fin and the upper surface of the isolation region, the gate structure comprising a gate dielectric layer and a gate electrode;
a dielectric layer adjacent to the first sidewall of the fin and the gate structure in a top-down view;
a spacer structure contacting a first sidewall of the gate structure;
a corner structure between the spacer structure and the gate structure on the first sidewall of the fin in the top-down view, wherein the corner structure is a separate element from the spacer structure, wherein the dielectric layer is between the corner structure and the fin; and
an epitaxial source/drain region adjacent to the gate structure.
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