US 12,426,326 B2
Semiconductor device
Ryohei Gejo, Kawasaki Kanagawa (JP)
Assigned to Kabushiki Kaisha Toshiba, Kawasaki (JP); and Toshiba Electronic Devices & Storage Corporation, Kawasaki (JP)
Filed by Kabushiki Kaisha Toshiba, Tokyo (JP); and Toshiba Electronic Devices & Storage Corporation, Tokyo (JP)
Filed on Feb. 3, 2023, as Appl. No. 18/164,426.
Claims priority of application No. 2022-145731 (JP), filed on Sep. 14, 2022.
Prior Publication US 2024/0088220 A1, Mar. 14, 2024
Int. Cl. H10D 62/10 (2025.01); H10D 12/00 (2025.01); H10D 84/60 (2025.01)
CPC H10D 62/127 (2025.01) [H10D 12/481 (2025.01); H10D 62/107 (2025.01); H10D 84/617 (2025.01)] 11 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a semiconductor layer having a first face and a second face facing the first face;
a first semiconductor region of a first conductive type provided in the semiconductor layer, in contact with the second face, and including a first portion having a first minimum width, a second portion having a second minimum width smaller than the first minimum width, and a third portion connecting the first portion and the second portion to each other and having a third minimum width smaller than the second minimum width;
a plurality of second semiconductor regions of a second conductive type provided in the semiconductor layer, in contact with the second face, and provided so as to be separated from each other in the first semiconductor region other than the first portion, the second portion, and the third portion;
a third semiconductor region of the second conductive type provided in the semiconductor layer and provided between the first semiconductor region and the first face and between the second semiconductor region and the first face;
a fourth semiconductor region of the first conductive type provided in the semiconductor layer and provided between the third semiconductor region and the first face;
a fifth semiconductor region of the second conductive type provided in the semiconductor layer and provided between the fourth semiconductor region and the first face;
a gate electrode facing the fourth semiconductor region;
a gate insulating film provided between the fourth semiconductor region and the gate electrode;
a first electrode in contact with the first face; and
a second electrode in contact with the second face.