US 12,426,324 B2
Gates structures of nanostructure field-effect transistors (nano-FETs) including a plurality of semiconductor based capping materials and methods of forming the same
Hsin-Yi Lee, Hsinchu (TW); Cheng-Lung Hung, Hsinchu (TW); and Chi On Chui, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 24, 2024, as Appl. No. 18/673,998.
Application 18/673,998 is a continuation of application No. 17/388,263, filed on Jul. 29, 2021, granted, now 12,021,116.
Claims priority of provisional application 63/196,980, filed on Jun. 4, 2021.
Prior Publication US 2024/0313050 A1, Sep. 19, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 62/10 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 62/13 (2025.01); H10D 62/17 (2025.01); H10D 64/01 (2025.01); H10D 84/83 (2025.01)
CPC H10D 62/121 (2025.01) [H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 62/151 (2025.01); H10D 62/235 (2025.01); H10D 64/018 (2025.01); H10D 84/834 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor device, the method comprising:
forming a first nanosheet over a substrate;
forming a second nanosheet over the first nanosheet, wherein the first nanosheet and the second nanosheet are disposed between source/drain regions, the source/drain regions being disposed over the substrate;
depositing a gate dielectric material around each of the first nanosheet and the second nanosheet;
depositing a work function material around the gate dielectric material;
forming a first capping material around the work function material, wherein the first capping material comprises silicon, and wherein a gap is disposed between the first capping material around the first nanosheet and the first capping material around the second nanosheet;
oxidizing the first capping material; and
forming a gate fill material over the first nanosheet and the second nanosheet.