US 12,426,323 B2
Semiconductor device including vertical transistor with back side power structure
Shih-Wei Peng, Hsinchu (TW); Te-Hsin Chiu, Hsinchu (TW); and Jiann-Tyng Tzeng, Hsin-Chu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Feb. 22, 2024, as Appl. No. 18/584,387.
Application 18/584,387 is a division of application No. 17/461,476, filed on Aug. 30, 2021, granted, now 11,948,974.
Prior Publication US 2024/0194734 A1, Jun. 13, 2024
Int. Cl. H10D 62/10 (2025.01); H01L 23/522 (2006.01); H01L 25/11 (2006.01); H10D 30/67 (2025.01)
CPC H10D 62/121 (2025.01) [H01L 23/5226 (2013.01); H01L 25/115 (2013.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 62/115 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor device including a plurality of cell structures, comprising:
forming, for each of the plurality of cell structures, a first source contact and a second source contact in a dielectric layer;
depositing, for each of the plurality of cell structures, a first source pad and a second source pad on the dielectric layer, wherein the first source pad and the second source pad are in contact with the first source contact and the second source contact, respectively;
depositing, for each of the plurality of cell structures, a gate pad on the first source pad and the second source pad;
forming a connection structure on the first source pad of a first cell structure, wherein the connection structure extends into a second cell structure adjacent to the first cell structure; and
depositing, for each of the plurality of cell structures, a first drain pad and a second drain pad on the gate pad, wherein the connection structure is electrically connected between the first drain pad of the second cell structure and the first source pad of the first cell structure.