US 12,426,321 B2
Transistor gate structures and methods of forming the same
Hsin-Yi Lee, Hsinchu (TW); Ji-Cheng Chen, Hsinchu (TW); Weng Chang, Hsinchu (TW); and Chi On Chui, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 19, 2022, as Appl. No. 17/867,804.
Claims priority of provisional application 63/363,587, filed on Apr. 26, 2022.
Prior Publication US 2023/0343822 A1, Oct. 26, 2023
Int. Cl. H01L 29/76 (2006.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01)
CPC H10D 62/121 (2025.01) [H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6757 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a first nanostructure;
a gate dielectric layer around the first nanostructure;
a first p-type work function tuning layer on the gate dielectric layer;
a dielectric barrier layer on the first p-type work function tuning layer, the dielectric barrier layer comprising silicon oxynitride; and
a second p-type work function tuning layer on the dielectric barrier layer, the dielectric barrier layer being thinner than the first p-type work function tuning layer and the second p-type work function tuning layer.