US 12,426,318 B2
Semiconductor device and method of manufacturing semiconductor device
Katsunori Danno, Obu (JP); and Tetsuya Shoji, Susono (JP)
Assigned to TOYOTA JIDOSHA KABUSHIKI KAISHA, Toyota (JP)
Filed by TOYOTA JIDOSHA KABUSHIKI KAISHA, Toyota (JP)
Filed on Jun. 30, 2022, as Appl. No. 17/854,142.
Claims priority of application No. 2021-114231 (JP), filed on Jul. 9, 2021; and application No. 2022-013261 (JP), filed on Jan. 31, 2022.
Prior Publication US 2023/0014283 A1, Jan. 19, 2023
Int. Cl. H10D 62/10 (2025.01); H01L 21/383 (2006.01); H01L 21/425 (2006.01); H10D 62/80 (2025.01); H10D 8/60 (2025.01)
CPC H10D 62/102 (2025.01) [H01L 21/383 (2013.01); H01L 21/425 (2013.01); H10D 62/80 (2025.01); H10D 8/60 (2025.01)] 14 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
an n-type gallium oxide semiconductor layer that has a center region and a peripheral region having a lower donor density than the center region;
an electrode layer that is laminated on the n-type gallium oxide semiconductor layer, and forms Schottky junction with the n-type gallium oxide semiconductor layer in the center region as viewed from a lamination direction; and
a first p-type nickel oxide semiconductor layer that is laminated on the n-type gallium oxide semiconductor layer such that the first p-type nickel oxide semiconductor layer is partially positioned between the n-type gallium oxide semiconductor layer and the electrode layer, and has an outer peripheral end portion on a peripheral region side in the peripheral region as viewed from the lamination direction,
wherein the first p-type nickel oxide semiconductor layer is positioned to straddle the center region and the peripheral region as viewed from the lamination direction.