US 12,426,316 B2
Method of fabricating integrated circuits with fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric material
Leonard Guler, Hillsboro, OR (US); Nick Lindert, Portland, OR (US); Biswajeet Guha, Hillsboro, OR (US); Swaminathan Sivakumar, Beaverton, OR (US); and Tahir Ghani, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 23, 2022, as Appl. No. 17/993,438.
Application 17/993,438 is a division of application No. 16/240,166, filed on Jan. 4, 2019, granted, now 11,538,937.
Prior Publication US 2023/0089815 A1, Mar. 23, 2023
Prior Publication US 2025/0176225 A2, May 29, 2025
Int. Cl. H10D 30/69 (2025.01); H01L 21/02 (2006.01); H01L 21/762 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01)
CPC H10D 30/798 (2025.01) [H01L 21/02238 (2013.01); H01L 21/76227 (2013.01); H10D 30/024 (2025.01); H10D 30/0243 (2025.01); H10D 30/62 (2025.01); H10D 30/6213 (2025.01); H10D 30/6219 (2025.01); H10D 30/795 (2025.01); H10D 62/116 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01); H10D 84/834 (2025.01)] 24 Claims
OG exemplary drawing
 
1. A method of fabricating an integrated circuit structure, the method comprising:
forming a fin comprising silicon;
exposing a portion of the fin;
etching the portion of the fin to form a trench separating a first fin portion and a second fin portion;
forming a layer comprising silicon in the trench;
forming an oxidation catalyst layer on the layer comprising silicon; and
oxidizing the layer comprising silicon in the presence of the oxidation catalyst layer.
 
4. A method of fabricating an integrated circuit structure, the method comprising:
forming a fin comprising silicon, the fin having a top and sidewalls, wherein the fin has a trench separating a first fin portion and a second fin portion;
forming a first gate structure comprising a gate electrode over the top of and laterally adjacent to the sidewalls of the first fin portion;
forming a second gate structure comprising a gate electrode over the top of and laterally adjacent to the sidewalls of the second fin portion; and
forming an isolation structure in the trench of the fin, the isolation structure between the first gate structure and the second gate structure, wherein the isolation structure comprises a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material, the recessed second dielectric material laterally surrounding an oxidation catalyst layer.
 
11. A method of fabricating an integrated circuit structure, the method comprising:
forming a fin comprising silicon, the fin having a top and sidewalls, wherein the top has a longest dimension along a direction;
forming a first isolation structure over a first end of the fin;
forming a gate structure comprising a gate electrode over the top of and laterally adjacent to the sidewalls of a region of the fin, wherein the gate structure is spaced apart from the first isolation structure along the direction; and
forming a second isolation structure over a second end of the fin, the second end opposite the first end, the second isolation structure spaced apart from the gate structure along the direction, wherein the first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material, the recessed second dielectric material laterally surrounding an oxidation catalyst layer.