US 12,426,314 B2
Strain generation and anchoring in gate-all-around field effect transistors
Julien Frougier, Albany, NY (US); Sung Dae Suk, Watervliet, NY (US); Kangguo Cheng, Schenectady, NY (US); Andrew M. Greene, Slingerlands, NY (US); and Ruilong Xie, Niskayuna, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Aug. 31, 2021, as Appl. No. 17/446,479.
Prior Publication US 2023/0065970 A1, Mar. 2, 2023
Int. Cl. H10D 30/69 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 62/10 (2025.01)
CPC H10D 30/751 (2025.01) [H10D 30/024 (2025.01); H10D 30/62 (2025.01); H10D 62/118 (2025.01); H10D 30/6219 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first source-drain having a first sidewall opposite a second sidewall, wherein the first sidewall of the first source-drain directly contacts end surfaces of a first set of semiconductor channel layers;
a second source-drain having a first sidewall opposite a second sidewall, wherein the first sidewall of the second source-drain directly contacts end surfaces of a second set of semiconductor channel layers; and
a single stressor component sandwiched between the first source-drain and the second source-drain, wherein the single stressor component directly contacts both the second sidewall of the first source-drain and the first sidewall of the second source-drain.