US 12,426,313 B2
Semiconductor device
Tatsuya Onuki, Kanagawa (JP); Munehiro Kozuma, Kanagawa (JP); Takeshi Aoki, Kanagawa (JP); Takanori Matsuzaki, Kanagawa (JP); Yuki Okamoto, Kanagawa (JP); Masashi Oota, Kanagawa (JP); Shuhei Nagatsuka, Kanagawa (JP); Hitoshi Kunitake, Kanagawa (JP); and Shunpei Yamazaki, Tokyo (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (JP)
Appl. No. 17/788,050
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
PCT Filed Dec. 14, 2020, PCT No. PCT/IB2020/061872
§ 371(c)(1), (2) Date Jun. 22, 2022,
PCT Pub. No. WO2021/130591, PCT Pub. Date Jul. 1, 2021.
Claims priority of application No. 2019-238710 (JP), filed on Dec. 27, 2019; application No. 2020-005295 (JP), filed on Jan. 16, 2020; and application No. 2020-169003 (JP), filed on Oct. 6, 2020.
Prior Publication US 2023/0040508 A1, Feb. 9, 2023
Int. Cl. H10D 30/67 (2025.01); G06N 3/02 (2006.01)
CPC H10D 30/6756 (2025.01) [G06N 3/02 (2013.01); H10D 30/673 (2025.01)] 13 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a CPU and an accelerator,
wherein the accelerator comprises a first memory circuit, a second memory circuit, and an arithmetic circuit,
wherein the first memory circuit comprises a first transistor,
wherein the second memory circuit comprises a second transistor,
wherein each of the first transistor and the second transistor comprises a semiconductor layer comprising a metal oxide in a channel formation region,
wherein the arithmetic circuit comprises a third transistor,
wherein the third transistor comprises a semiconductor layer comprising silicon in a channel formation region,
wherein the CPU comprises a CPU core comprising a flip-flop provided with a backup circuit,
wherein the backup circuit comprises a fourth transistor,
wherein the fourth transistor comprises a semiconductor layer comprising a metal oxide in a channel formation region,
wherein the first transistor and the second transistor are provided in different layers, and
wherein the layer comprising the first transistor and the layer comprising the second transistor are provided over a layer comprising the third transistor.