US 12,426,306 B2
Semiconductor device having light-emitting element
Shunpei Yamazaki, Tokyo (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Dec. 28, 2023, as Appl. No. 18/398,373.
Application 18/398,373 is a continuation of application No. 17/982,566, filed on Nov. 8, 2022, granted, now 11,869,977.
Application 17/982,566 is a continuation of application No. 17/062,697, filed on Oct. 5, 2020, granted, now 11,508,852, issued on Nov. 22, 2022.
Application 17/062,697 is a continuation of application No. 15/614,694, filed on Jun. 6, 2017, granted, now 10,797,179, issued on Oct. 6, 2020.
Application 15/614,694 is a continuation of application No. 14/391,024, granted, now 9,680,026, issued on Jun. 13, 2017, previously published as PCT/JP2014/074155, filed on Sep. 5, 2014.
Claims priority of application No. 2013-190275 (JP), filed on Sep. 13, 2013.
Prior Publication US 2024/0258433 A1, Aug. 1, 2024
Int. Cl. H10D 30/67 (2025.01); G02F 1/1368 (2006.01); H10D 30/62 (2025.01)
CPC H10D 30/6734 (2025.01) [H10D 30/62 (2025.01); H10D 30/6219 (2025.01); H10D 30/6729 (2025.01); H10D 30/675 (2025.01); H10D 30/6757 (2025.01); G02F 1/1368 (2013.01)] 2 Claims
OG exemplary drawing
 
2. A light-emitting device comprising:
a first transistor in a pixel;
a second transistor in the pixel;
a light-emitting element in the pixel;
a capacitor in the pixel;
a wiring to which an image signal is input in the pixel; and
a power source line in the pixel,
wherein one of a source and a drain of the first transistor is always conductive to the wiring,
wherein the first transistor is configured to control an input of the image signal to the pixel,
wherein the second transistor is configured to control a current supplied from the power source line to the light-emitting element in response to the image signal,
wherein a first conductive film is configured to be a gate electrode of the second transistor,
wherein a second conductive film is always conductive to a third conductive film,
wherein the second conductive film and the third conductive film are configured to be the power source line,
wherein a fourth conductive film is configured to be the wiring,
wherein a fifth conductive film is configured to be a first electrode of the capacitor,
wherein a sixth conductive film is configured to be a gate electrode of the first transistor,
wherein a semiconductor film which includes a channel formation region of the first transistor comprises a first region which overlaps the fifth conductive film,
wherein the first region is configured to be a second electrode of the capacitor,
wherein a channel formation region of the second transistor has a bent shape,
wherein the first conductive film is provided over the channel formation region of the second transistor so that the first conductive film overlaps the channel formation region of the second transistor,
wherein the second conductive film is provided over the third conductive film so as to intersect with the third conductive film,
wherein the second conductive film is provided over the sixth conductive film so as to intersect with the sixth conductive film,
wherein the fourth conductive film is provided over the third conductive film so as to intersect with the third conductive film,
wherein the second conductive film and the fourth conductive film are in a first layer, and
wherein the third conductive film and the fifth conductive film are in a second layer.