US 12,426,303 B2
Semiconductor device including insulation gate-type transistors
Hajime Okuda, Kyoto (JP); Yoshinori Fukuda, Kyoto (JP); Toru Takuma, Kyoto (JP); Shuntaro Takahashi, Kyoto (JP); and Naoki Takahashi, Kyoto (JP)
Assigned to ROHM CO., LTD., Kyoto (JP)
Appl. No. 17/414,722
Filed by ROHM CO., LTD., Kyoto (JP)
PCT Filed Dec. 20, 2019, PCT No. PCT/JP2019/050173
§ 371(c)(1), (2) Date Jun. 16, 2021,
PCT Pub. No. WO2020/130141, PCT Pub. Date Jun. 25, 2020.
Claims priority of application No. 2018-240076 (JP), filed on Dec. 21, 2018; and application No. 2019-026833 (JP), filed on Feb. 18, 2019.
Prior Publication US 2022/0045208 A1, Feb. 10, 2022
Int. Cl. H10D 30/66 (2025.01); H01L 21/76 (2006.01); H10D 12/00 (2025.01); H10D 62/17 (2025.01); H10D 64/27 (2025.01); H10D 30/65 (2025.01); H10D 30/69 (2025.01); H10D 62/13 (2025.01); H10D 88/00 (2025.01)
CPC H10D 30/668 (2025.01) [H01L 21/76 (2013.01); H10D 12/481 (2025.01); H10D 62/393 (2025.01); H10D 64/519 (2025.01); H10D 30/658 (2025.01); H10D 30/699 (2025.01); H10D 62/157 (2025.01); H10D 64/512 (2025.01); H10D 64/513 (2025.01); H10D 88/00 (2025.01); H10D 88/101 (2025.01)] 8 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a semiconductor layer including a main surface;
a first transistor of an insulation gate-type which is formed in the semiconductor layer;
a second transistor of an insulation gate-type which is formed in the semiconductor layer; and
a control wiring, which is formed on the semiconductor layer such as to be electrically connected to the first transistor and the second transistor, configured to transmit control signals that control the first transistor and the second transistor to be in ON states in a normal operation and that control the first transistor to be in an OFF state and the second transistor to be in an ON state in an active clamp operation, wherein
the control wiring includes a first control wiring which is electrically connected to the first transistor and a second control wiring which is electrically connected to the second transistor in a state of being electrically insulated from the first transistor,
the first transistor includes a first trench gate structure which has a first insulation layer in contact with the semiconductor layer and a first electrode facing the semiconductor layer across the first insulation layer,
the second transistor includes a second trench gate structure which has a second insulation layer in contact with the semiconductor layer and a second electrode facing the semiconductor layer across the second insulation layer,
during the normal operation, the first transistor and the second transistor are each controlled to be in the ON states via the first control wiring and the second control wiring, respectively, and
during the active clamp operation, the first transistor is controlled to be in the OFF state via the first control wiring, while the second transistor is controlled to be in the ON state via the second control wiring.