US 12,426,302 B2
Semiconductor devices and methods of manufacturing semiconductor device
Yuan Liang Liu, Hsinchu County (TW); Yi Chen Lee, Hsinchu County (TW); and Yen Chang Chen, Hsinchu County (TW)
Assigned to EPISIL TECHNOLOGIES INC., Hsinchu Country (TW)
Filed by EPISIL TECHNOLOGIES INC., Hsinchu County (TW)
Filed on Jan. 18, 2023, as Appl. No. 18/098,205.
Claims priority of application No. 111110474 (TW), filed on Mar. 22, 2022.
Prior Publication US 2023/0307497 A1, Sep. 28, 2023
Int. Cl. H10D 12/01 (2025.01); H10D 30/66 (2025.01); H10D 62/832 (2025.01); H10D 64/23 (2025.01); H10D 62/10 (2025.01)
CPC H10D 30/665 (2025.01) [H10D 12/031 (2025.01); H10D 62/8325 (2025.01); H10D 64/256 (2025.01); H10D 62/106 (2025.01)] 5 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor device comprising:
sequentially depositing a gate oxide layer, a poly silicon layer and a first oxide layer on a SiC epitaxial layer, wherein a p-type well region is disposed in the SiC epitaxial layer, a heavily doped n-type region is disposed on a surface of the p-type well region, and a heavily doped p-type region is disposed below the heavily doped n-type region and within the p-type well region;
after gate pattern definition, etching the first oxide layer and the poly silicon layer and stopping etching at the gate oxide layer, wherein a portion of the heavily doped n-type region overlaps with the poly silicon layer;
depositing a second oxide layer on the first oxide layer and the heavily doped n-type region;
etching the second oxide layer by a first blanket etch process to expose the first oxide layer and the heavily doped n-type region;
forming a first recess in a source region by a second blanket etch process, wherein a depth of the first recess exceeds a depth of the heavily doped n-type region.