	US 12,426,291 B2
	Contact and via structures for semiconductor devices
Mrunal A. Khaderbad, Hsinchu (TW); and Keng-Chu Lin, Ping-Tung (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 1, 2022, as Appl. No. 17/856,179.
Application 17/856,179 is a division of application No. 16/717,600, filed on Dec. 17, 2019, granted, now 11,380,781.
Prior Publication US 2022/0336642 A1, Oct. 20, 2022
Int. Cl. H10D 30/01 (2025.01); H01L 21/768 (2006.01); H10D 30/62 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)

CPC H10D 30/024 (2025.01) [H01L 21/76805 (2013.01); H01L 21/76831 (2013.01); H01L 21/76877 (2013.01); H10D 30/6211 (2025.01); H10D 30/6219 (2025.01); H10D 64/01 (2025.01); H10D 84/013 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01)]

20 Claims

1. A method, comprising:

forming an epitaxial source/drain (S/D) region within a substrate;

forming a contact structure on the epitaxial S/D region;

forming a dielectric layer on the contact structure;

forming a via opening in the dielectric layer and on the contact structure;

forming a non-metal passivation layer, on sidewalls of the via opening, comprising:

depositing a non-metal passivation material at a substantially constant deposition rate; and

etching the non-metal passivation material on the sidewalls of the via opening at an etch rate that increases from a top of the via opening to a bottom of the via opening; and

depositing a conductive plug using a bottom-up deposition process to fill the via opening.