US 12,426,289 B2
Semiconductor device
Shigeki Sato, Azumino (JP); Soichi Yoshida, Matsumoto (JP); Kouji Asahi, Shiojiri (JP); and Seiji Momota, Matsumoto (JP)
Assigned to FUJI ELECTRIC CO., LTD., Kanagawa (JP)
Filed by FUJI ELECTRIC CO., LTD., Kanagawa (JP)
Filed on Feb. 24, 2022, as Appl. No. 17/680,270.
Claims priority of application No. 2021-065973 (JP), filed on Apr. 8, 2021.
Prior Publication US 2022/0328668 A1, Oct. 13, 2022
Int. Cl. H10D 12/00 (2025.01); G01K 7/01 (2006.01); H01L 23/528 (2006.01); H10D 62/10 (2025.01); H10D 64/27 (2025.01)
CPC H10D 12/481 (2025.01) [G01K 7/01 (2013.01); H01L 23/528 (2013.01); H10D 62/127 (2025.01); H10D 64/519 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first trench having a predetermined first trench length;
a second trench having a second trench length longer than the first trench length;
a first gate runner configured to be electrically connected to an end of the first trench; and
a second gate runner configured to be electrically connected to the first gate runner and electrically connected to an end of the second trench, wherein
a resistivity per unit length of the first gate runner is larger than a resistivity per unit length of the second gate runner.