US 12,426,287 B2
Semiconductor device
Akihiro Tanaka, Himeji Hyogo (JP); Tetsuhiro Saisho, Himeji Hyogo (JP); Toru Shono, Himeji Hyogo (JP); and Koji Onishi, Ibo Hyogo (JP)
Assigned to Kabushiki Kaisha Toshiba, Kawasaki (JP); and Toshiba Electronic Devices & Storage Corporation, Kawasaki (JP)
Filed by KABUSHIKI KAISHA TOSHIBA, Tokyo (JP); and TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION, Tokyo (JP)
Filed on Aug. 24, 2021, as Appl. No. 17/410,937.
Claims priority of application No. 2020-155203 (JP), filed on Sep. 16, 2020; and application No. 2021-118602 (JP), filed on Jul. 19, 2021.
Prior Publication US 2022/0085192 A1, Mar. 17, 2022
Int. Cl. H10D 12/00 (2025.01); H10D 62/10 (2025.01)
CPC H10D 12/481 (2025.01) [H10D 62/125 (2025.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a semiconductor part including
an outer perimeter,
a first region,
a second region positioned between the first region and the outer perimeter,
a first semiconductor layer of an n-type,
a second semiconductor layer provided on the first semiconductor layer, the second semiconductor layer being of a p-type,
a third semiconductor layer provided on the second semiconductor layer, the third semiconductor layer being of the n-type, and
a fourth semiconductor layer provided on the second semiconductor layer, the fourth semiconductor layer being of the p-type and having a higher p-type impurity concentration than the second semiconductor layer,
a ratio of a surface area of the fourth semiconductor layer to a surface area of the third semiconductor layer in the second region being greater than a ratio of a surface area of the fourth semiconductor layer to a surface area of the third semiconductor layer in the first region;
a gate electrode provided in the semiconductor part, the gate electrode including a side surface facing the second semiconductor layer;
an insulating film provided between the semiconductor part and the side surface of the gate electrode; and
an upper electrode provided on the semiconductor part, the upper electrode contacting the third and fourth semiconductor layers, wherein
the fourth semiconductor layer includes:
a first portion located in the first region;
a second portion located in the second region; and
a third portion located in the second region, the third portion linking the first portion and the second portion, and
a width of the second portion and a width of the third portion are greater than a width of the first portion.