US 12,426,282 B2
Method of forming capacitor hole, and semiconductor structure
Yulei Wu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Sep. 27, 2022, as Appl. No. 17/935,630.
Application 17/935,630 is a continuation of application No. PCT/CN2021/127617, filed on Oct. 29, 2021.
Claims priority of application No. 202110758236.1 (CN), filed on Jul. 5, 2021.
Prior Publication US 2023/0019605 A1, Jan. 19, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 1/00 (2025.01); H01L 21/033 (2006.01); H01L 21/311 (2006.01); H10D 1/68 (2025.01)
CPC H10D 1/043 (2025.01) [H01L 21/0337 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H10D 1/696 (2025.01); H10D 1/716 (2025.01)] 14 Claims
OG exemplary drawing
 
1. A method of forming a capacitor hole, comprising:
providing a substrate, wherein an electrode is formed in the substrate;
forming a pattern definition layer on a surface of the substrate;
sequentially forming three sets of trenches in the pattern definition layer, wherein the three sets of trenches intersect with each other at 120°, and a hexagonal hole is formed at an intersection position in the pattern definition layer; and
etching the substrate along the hexagonal hole by the pattern definition layer as a mask, to form a capacitor hole in the substrate, wherein a bottom of the capacitor hole is round under a loading effect of etching, and the electrode is exposed at the bottom of the capacitor hole.