US 12,426,280 B2
Semiconductor structure with increased number of stacked memory dies and method of manufacturing the same
Ling-Yi Chuang, Hefei (CN); and Kaimin Lv, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Feb. 3, 2023, as Appl. No. 18/164,235.
Claims priority of application No. 202210959583.5 (CN), filed on Aug. 10, 2022.
Prior Publication US 2024/0057351 A1, Feb. 15, 2024
Int. Cl. H10B 80/00 (2023.01)
CPC H10B 80/00 (2023.02) 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a logic die provided with a first wireless communication component;
a plurality of memory components arrayed in a first direction and stacked on an upper surface of the logic die, wherein the first direction is parallel to the upper surface of the logic die; and
a first adhesive film arranged between any two adjacent memory components of the plurality of memory components and adhered to the any two adjacent memory components,
wherein each of the plurality of memory components comprises a plurality of memory dies arrayed in the first direction, wherein each of the plurality of memory dies is provided with a second wireless communication component, wherein the second wireless communication component is in wireless communication with the first wireless communication component, and
wherein at least one of the plurality of memory dies is provided with a power supply wiring layer, wherein the power supply wiring layer extends towards the logic die along an active surface of the at least one of the plurality of memory dies;
wherein each of the memory dies is provided with a plurality of power supply signal lines, and the power supply wiring layer is electrically connected to the plurality of power supply signal lines;
an end surface of the power supply wiring layer facing towards the logic die is exposed by the at least one of the plurality of memory dies;
the at least one of the plurality of memory dies is further provided with a welding bump, wherein the welding bump is connected to the end surface; and
the logic die is provided with a power supply port, wherein the power supply port is electrically connected to the welding bump;
wherein each of the plurality of memory dies is provided with the power supply wiring layer;
wherein a plurality of welding bumps are connected to the same power supply wiring layer, and the plurality of welding bumps are arranged in a second direction and spaced apart from each other, wherein the second direction is parallel to the upper surface of the logic die and perpendicular to the first direction; and
wherein the plurality of welding bumps connected to one power supply wiring layer are misaligned, in the first direction, with the plurality of welding bumps connected to another power supply wiring layer adjacent to the one power supply wiring layer.