US 12,426,276 B2
Semiconductor device, memory cell and method of forming the same
Yu-Chao Lin, Hsinchu (TW); and Tung-Ying Lee, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 2, 2022, as Appl. No. 17/830,352.
Prior Publication US 2023/0397439 A1, Dec. 7, 2023
Int. Cl. H10B 63/00 (2023.01); H01L 23/528 (2006.01); H10N 70/00 (2023.01)
CPC H10B 63/24 (2023.02) [H01L 23/5283 (2013.01); H10N 70/063 (2023.02); H10N 70/841 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory cell, comprising:
a selector disposed over a substrate, wherein the selector comprises:
a bottom electrode;
an ovonic threshold switch layer on the bottom electrode;
an inter-electrode over the ovonic threshold switch layer; and
an intermediate layer between the ovonic threshold switch layer and the inter-electrode, wherein the intermediate layer has a curved sidewall extending from a top surface of the ovonic threshold switch layer to a bottom surface of the inter-electrode;
a memory element disposed on the selector; and
a connecting pad disposed on the memory element.