US 12,426,274 B2
Method for MRAM top electrode connection
Harry-Hak-Lay Chuang, Zhubei (TW); Hung Cho Wang, Taipei (TW); Sheng-Chang Chen, Hsinchu County (TW); and Sheng-Huang Huang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jan. 10, 2024, as Appl. No. 18/408,892.
Application 18/408,892 is a division of application No. 17/703,065, filed on Mar. 24, 2022, granted, now 11,910,619.
Application 17/703,065 is a continuation of application No. 16/884,353, filed on May 27, 2020, granted, now 11,322,543, issued on May 3, 2022.
Prior Publication US 2024/0147734 A1, May 2, 2024
Int. Cl. H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/80 (2023.01)
CPC H10B 61/22 (2023.02) [H10N 50/01 (2023.02); H10N 50/80 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
a memory cell overlying a substrate and comprising a top electrode;
a sidewall spacer structure disposed along sidewalls of the memory cell, wherein the sidewall spacer structure comprises a first spacer layer on the memory cell, a second spacer layer around the first spacer layer, and a third spacer layer around the second spacer layer, wherein the second spacer layer comprises a lateral segment adjacent to a vertical segment, wherein the lateral segment abuts the top electrode and has a top surface aligned with or disposed below a top surface of the top electrode; and
a first conductive structure overlying the memory cell and contacting the lateral segment and the top electrode.