US 12,426,265 B2
Method used in forming a memory array comprising strings of memory cells using pillars
John D. Hopkins, Meridian, ID (US); and Nancy M. Lomeli, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 6, 2024, as Appl. No. 18/597,695.
Application 18/597,695 is a division of application No. 17/150,322, filed on Jan. 15, 2021, granted, now 11,956,955.
Prior Publication US 2024/0251556 A1, Jul. 25, 2024
Int. Cl. H10B 43/27 (2023.01); H01L 21/225 (2006.01); H10B 41/27 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 21/2254 (2013.01); H10B 41/27 (2023.02)] 14 Claims
OG exemplary drawing
 
1. A method used in forming a memory array comprising strings of memory cells, comprising:
forming a conductor tier comprising conductor material on a substrate;
forming a lower portion stack that will comprise vertically-alternating first tiers and second tiers above the conductor tier, the stack comprising laterally-spaced memory-block regions, material of the first tiers being of different composition from material of the second tiers, a lowest of the first tiers in the lower portion comprising sacrificial material;
forming pillars in the lower portion that are individually horizontally-located where individual channel-material strings will be formed, individual of the pillars comprising a laterally-inner material and a liner laterally-outward of the laterally-inner material, the liner extending upwardly above the sacrificial material;
forming the vertically-alternating first tiers and second tiers of an upper portion of the stack above the lower portion and the pillars;
forming channel openings into the stack that individually extend to the individual pillars;
removing the laterally-inner material of the pillars through the channel openings to extend the channel openings deeper into the stack;
forming individual of the channel-material strings in individual of the extended channel openings and in voids therein resulting from said removing and laterally-inward of individual of the liners;
forming horizontally-elongated trenches into the stack that are individually between immediately-laterally-adjacent of the memory-block regions and extend to the lowest first tier;
isotropically etching the sacrificial material from the lowest first tier through the trenches to expose the liners, the liners before and after the isotropically etching individually having their uppermost surface above the conductor tier, below a bottom of an uppermost of the first tiers, and below uppermost surfaces of the individual channel-material strings;
isotropically etching the exposed liners to form void-spaces above the lowest first tier that are individually laterally-between the individual channel-material strings and the second-tier material that is in the second tier that is immediately-below the lowest first tier that is in the upper portion;
forming conductively-doped semiconductive material against sidewalls of the channel material of the channel-material strings that directly electrically couples together the channel material of the individual channel-material strings and the conductor material of the conductor tier, the conductively-doped semiconductive material extending upwardly into the void-spaces; and
heating the conductively-doped semiconductive material to diffuse conductivity-increasing dopants therein from the void-spaces laterally into the channel material laterally there-adjacent and upwardly into the channel material that is above the void-spaces.