US 12,426,262 B2
Charge storage apparatus and methods
Sanh D. Tang, Boise, ID (US); and John K. Zahurak, Eagle, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 13, 2023, as Appl. No. 18/108,970.
Application 14/310,790 is a division of application No. 13/035,700, filed on Feb. 25, 2011, granted, now 8,759,895.
Application 18/108,970 is a continuation of application No. 16/813,332, filed on Mar. 9, 2020, granted, now 11,581,324.
Application 16/813,332 is a continuation of application No. 15/691,442, filed on Aug. 30, 2017, granted, now 10,586,802.
Application 15/691,442 is a continuation of application No. 14/987,370, filed on Jan. 4, 2016, granted, now 9,754,953.
Application 14/987,370 is a continuation of application No. 14/310,790, filed on Jun. 20, 2014, granted, now 9,231,117.
Prior Publication US 2023/0269937 A1, Aug. 24, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 41/23 (2023.01); H10B 41/27 (2023.01); H10B 41/30 (2023.01); H10B 41/35 (2023.01); H10B 43/20 (2023.01); H10B 43/27 (2023.01); H10D 30/68 (2025.01); H10D 30/69 (2025.01); H10D 62/40 (2025.01); H10D 62/834 (2025.01); H10D 64/01 (2025.01); H10D 64/66 (2025.01)
CPC H10B 41/27 (2023.02) [H10B 41/30 (2023.02); H10B 41/35 (2023.02); H10B 43/20 (2023.02); H10B 43/27 (2023.02); H10D 30/689 (2025.01); H10D 30/69 (2025.01); H10D 62/40 (2025.01); H10D 62/834 (2025.01); H10D 64/035 (2025.01); H10D 64/037 (2025.01); H10D 64/665 (2025.01); H10D 64/667 (2025.01); H10D 30/693 (2025.01)] 11 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a silicon channel material forming a channel for multiple memory cells in a string of NAND memory cells;
a first charge storage structure of a first memory cell in the string of NAND memory cells, the first charge storage structure at least partially surrounding the silicon channel material in a first tier;
a second charge storage structure of a second memory cell of the string of NAND memory cells, the second charge storage structure surrounding the silicon channel material in a second tier;
a first dielectric structure having a first surface in contact with the first charge storage structure and the second charge storage structure, and having an opposing surface in contact with the silicon channel material;
wherein the first and second memory cells comprise at least a portion of first and second word lines, the first and second word lines each having a respective planar vertical end surface facing the respective first and second charge storage structures;
a second dielectric structure extending horizontally between the first and second word lines, wherein each of the first and second charge storage structures contacts the horizontally extending second dielectric structure;
a third dielectric structure extending between the first word line and the first charge storage structure, wherein a vertical dimension of the third dielectric structure is greater than a vertical dimension of the first word line; and
a fourth dielectric structure extending between the second word line and the second charge storage structure, wherein a vertical dimension of the fourth dielectric structure is greater than a vertical dimension of the second word line.