US 12,426,261 B2
Integrated circuitry comprising a memory array comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
Daniel Billingsley, Meridian, ID (US); Jordan D. Greenlee, Boise, ID (US); John D. Hopkins, Meridian, ID (US); Yongjun Jeff Hu, Boise, ID (US); and Swapnil Lengade, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 7, 2022, as Appl. No. 18/076,702.
Application 18/076,702 is a division of application No. 17/068,470, filed on Oct. 12, 2020, granted, now 11,552,090.
Claims priority of provisional application 63/071,563, filed on Aug. 28, 2020.
Prior Publication US 2023/0099418 A1, Mar. 30, 2023
Int. Cl. H10B 41/27 (2023.01); G11C 16/04 (2006.01); H10B 41/10 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01)
CPC H10B 41/27 (2023.02) [G11C 16/0483 (2013.01); H10B 41/10 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] 18 Claims
OG exemplary drawing
 
1. Integrated circuitry comprising a memory array comprising strings of memory cells, comprising:
an upper stack directly above a lower stack, the lower stack comprising vertically-alternating lower-conductive-tiers and lower-insulative-tiers, the upper stack comprising vertically-alternating upper-conductive-tiers and upper-insulative-tiers;
an upper tier of the lower-insulative-tiers or a lower tier of the upper-insulative-tiers comprising non-stoichiometric silicon dioxide having a silicon-to-oxygen atomic ratio greater than 0.5, a higher tier of the upper-insulative-tiers that is above said lower upper-insulative-tier comprising silicon dioxide having a silicon-to-oxygen atomic ratio less than or equal to 0.5; and
channel-material strings of memory cells extending through the upper stack and the lower stack including through the non-stoichiometric silicon dioxide.