US 12,426,256 B2
Semiconductor structure including a plurality of semicondcutor pillars and bit line isolation trenches and method for forming same
Guangsu Shao, Hefei (CN); Deyuan Xiao, Hefei (CN); Yunsong Qiu, Hefei (CN); and Minmin Wu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN); and BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY, Beijing (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN); and BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY, BeiJing (CN)
Filed on Jul. 4, 2022, as Appl. No. 17/810,634.
Application 17/810,634 is a continuation of application No. PCT/CN2022/077727, filed on Feb. 24, 2022.
Claims priority of application No. 202110941165.9 (CN), filed on Aug. 17, 2021.
Prior Publication US 2023/0057480 A1, Feb. 23, 2023
Int. Cl. H01L 21/762 (2006.01); H01L 21/311 (2006.01); H10B 12/00 (2023.01); G11C 7/18 (2006.01)
CPC H10B 12/482 (2023.02) [H01L 21/31116 (2013.01); H01L 21/76224 (2013.01); H10B 12/053 (2023.02); H10B 12/30 (2023.02); H10B 12/488 (2023.02); G11C 7/18 (2013.01); H10B 12/485 (2023.02)] 11 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor device, comprising:
providing a semiconductor substrate comprising a plurality of first semiconductor pillars and bit line isolation trenches arranged at intervals in a first direction; wherein the bit line isolation trenches extend in a second direction, and the first direction is perpendicular to the second direction;
forming a bit line isolation layer in at least one of the bit line isolation trenches; wherein a gap is provided between the bit line isolation layer and the at least one of the bit line isolation trenches, wherein the gap is located at a bottom corner of the at least one of the bit line isolation trenches and extends in the second direction, and the gap exposes part of a bottom of the at least one of the bit line isolation trenches;
etching at least one of the first semiconductor pillars in the first direction through the gap to form the one of the at least a bit line trenches; and
forming a bit line in the at least one of the bit line trenches;
wherein forming the bit line isolation layer in at least one of the bit line isolation trenches comprises:
forming an initial bit line isolation layer in at least one of the bit line isolation trenches; and
removing part of the initial bit line isolation layer to form the bit line isolation layer and the gap;
wherein forming the initial bit line isolation layer in at least one of the bit line isolation trenches comprises:
forming a first initial isolation layer and a second initial isolation layer in sequence in at least one of the bit line isolation trenches;
removing part of the second initial isolation layer and part of the first initial isolation layer in sequence by etching in a third direction to form a first etching groove; wherein the first etching groove exposes a first sidewall of at least one of the bit line isolation trenches and another part of the bottom of at least one of the bit line isolation trenches; and the third direction is a depth direction of at least one of the bit line isolation trenches; and
filling an isolation material in the first etching groove to form a third initial isolation layer,
wherein remaining first initial isolation layer, remaining second initial isolation layer and the third initial isolation layer constitute the initial bit line isolation layer.