US 12,426,255 B2
Semiconductor structure, method for manufacturing semiconductor structure, and memory
Guangsu Shao, Hefei (CN); and Deyuan Xiao, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Sep. 21, 2022, as Appl. No. 17/949,987.
Application 17/949,987 is a continuation of application No. PCT/CN2022/105112, filed on Jul. 12, 2022.
Claims priority of application No. 202210709198.5 (CN), filed on Jun. 21, 2022.
Prior Publication US 2023/0016905 A1, Jan. 19, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/39 (2023.02) [H10B 12/0385 (2023.02); H10B 12/0387 (2023.02); H10B 12/053 (2023.02)] 15 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising: a plurality of first semiconductor pillars, a plurality of second semiconductor pillars, a first support layer, a storage structure, and a plurality of transistors,
wherein the plurality of first semiconductor pillars are arranged in an array in a first direction and in a second direction, each of the first direction and the second direction is perpendicular to an extending direction of each of the plurality of first semiconductor pillars, and the first direction intersects with the second direction;
wherein the first support layer covers sidewalls of top portions of the plurality of first semiconductor pillars;
wherein each of the plurality of second semiconductor pillars is arranged on and in contact with a respective one of the plurality of first semiconductor pillars, and the storage structure is arranged around sidewalls of the plurality of first semiconductor pillars and sidewalls of lower portions of the plurality of second semiconductor pillars; and
wherein a channel structure of each of the plurality of transistors arranged in an upper portion of a respective one of the plurality of second semiconductor pillars, and an extending direction of the channel structure is perpendicular to a plane where the first direction and the second direction are located,
wherein each of the plurality of transistors comprises:
a gate structure arranged around a portion of a sidewall of the upper portion of the respective one of the plurality of second semiconductor pillars;
a source arranged in the upper portion of the respective one of the plurality of second semiconductor pillars and arranged at one end of the channel structure; and
a drain arranged in the upper portion of the respective one of the plurality of second semiconductor pillars that arranged at another end of the channel structure.