| CPC H10B 12/37 (2023.02) [H10D 1/042 (2025.01); H10D 1/714 (2025.01); H10D 1/716 (2025.01)] | 18 Claims |
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1. A semiconductor structure, comprising:
a substrate comprising a capacitor region;
a first isolation structure disposed in the substrate in the capacitor region; and
a capacitor, located in the capacitor region, and comprising:
the substrate in the capacitor region;
an electrode layer disposed in the substrate in the capacitor region; and
a first dielectric layer disposed between the electrode layer and the substrate and between the electrode layer and the first isolation structure, wherein the first dielectric layer is in direct contact with the first isolation structure,
wherein the substrate further comprises a memory cell region, and the semiconductor structure further comprises:
a second isolation structure disposed in the substrate in the memory cell region;
a gate electrode disposed in the substrate in the memory cell region; and
a second dielectric layer disposed between the gate electrode and the substrate and between the gate electrode and the second isolation structure, wherein the second dielectric layer is in direct contact with the second isolation structure.
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